SSI operating principle of absolute encoder！

In rest conditions, the CLOCK and DATA lines are at a high logical level and the mono-stable circuit is disabled (high level).

1. On the first CLOCK signal descent front, the mono-stable is activated and the parallel value present at the input to the
 P/S converter is memorised in the shift register.
2. On the CLOCK signal ascent front, the most significant bit (MSB) is placed in the output on the DATA line.
3. On the CLOCK descent front when the signal is stable the controller acquires the level from the DATA line, which is the
 value of the most significant bit, the mono-stable is re-activated.
4. On each further ascent front of the CLOCK impulse sequence, the successive bits up to the least significant one are
 place in the output on the DATA line and acquired by the control on the descent front.

absolute encoder, incremental encoder, hybrid encoder, non-magnetic encoder, multi-turn encoder, multi-turn combination encoder, draw wire encoder, digital readout, linear scale
5.At the end of the CLOCK impulse sequence when the external control has also acquired the value of the least significant
 (LSB) the CLOCK impulse sequence is interrupted and therefore the mono-stable is no longer re-activated.
6.Once the mono-stable time (Tm) has elapsed, the DATA line returns to a high logical level and the mono-stable disables
itself.

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